The present invention relates to a semiconductor device and, more particularly, to a semiconductor device which applies stress to a test circuit to be subjected to a burn-in test, using plural flip-flops which are connected in a scan chain.
In recent years, as the scale of semiconductor devices has been increased, reliability tests such as a burn-in test have become more important. However, when testing a large-scale semiconductor device, it is very difficult to realize 100% of the actual operation state of the semiconductor device on a set device, by a combination of prepared signal sources. Therefore, a burn-in test or the like is carried out by applying stress to a circuit to be tested, utilizing a scan design method. The simulation stress application using the scan design method is carried out as follows. An equivalent test pattern is formed by the scan design method, and stress is applied to the test pattern to realize a circuit operation rate equivalent to that in the actual operation mode, with a restricted pattern length. Thereby, when a semiconductor device is subjected to a reliability test or the like, the ratio of operating circuits in the semiconductor device can be brought close to that in the actual operation state, although it is not equivalent to the actual operation state.
Hereinafter, a description will be given of a burn-in test using scan chains in a conventional semiconductor device.
First of all, the construction of a conventional semiconductor device will be described with reference to FIG. 10. In FIG. 10, a semiconductor device 1 comprises a memory 2, scan chains 14a and 14b each comprising plural flip-flops 11, combinational circuits 12, and a clock generation circuit 13 for outputting a clock signal 105. The scan chains 14a and 14b have first and second scan input terminals 16 and 17 to which input signals 101 and 102 are applied, and first and second scan output terminals 18 and 19 from which output signals 103 and 104 are outputted, respectively. A scan chain is a chain of flip-flops which are connected such that an output for scanning from a previous-stage flip-flop becomes a normal input to a subsequent-stage flip-flop when performing a scan test.
In the semiconductor device 1 constructed as described above, when performing a test using the scan chains 14a and 14b, since the plural flip-flops 11 are chain-connected from the scan input terminals 16 and 17 to the scan output terminals 18 and 19 in the scan chains 14a and 14b, respectively, desired data values can be set on arbitrary flip-flops by inputting the signals 101 and 102 to the scan input terminals 16 and 17 when performing a scan test (hereinafter referred to as xe2x80x9cscan shiftxe2x80x9d). After the setting of data values is completed, the combinational circuits 12 are operated by the normal operation of the semiconductor device 1 to perform a scan shift, whereby stress is applied to the memory 2 which is a target circuit to be tested in the semiconductor device 1. At this time, the values of the output signals 103 and 104 from the scan output terminals 18 and 19 are compared with a predetermined expected value, thereby performing a circuit test in the semiconductor device 1. A test comprising a series of operations as described above is called a scan shift or a burn-in test using scan chains.
When subjecting the semiconductor device 1 to a burn-in test using scan chains, the above-described scan shift and normal operation are repeated, whereby the target circuit to be tested in the semiconductor device 1 is operated more actively to give greater stress to the circuit, thereby testing the reliability of the semiconductor device 1.
In the conventional semiconductor device 1 constructed as described above, however, since the outputs from the respective flip-flops 11 in the scan chains 14a and 14b are inputted to the memory 2 as a target circuit to be tested through the combinational circuits 12, the desired data values inputted from the scan input terminals 16 and 17 might be changed in the combinational circuits 12, depending on the constructions of the combinational circuits 12, to become undefined values, resulting in difficulty in controlling the memory 2 during the test. This makes it difficult to apply stress to the whole memory 2 and, at the worst, no stress might be applied to the memory 2.
As a solution to the above-described problem, there is proposed a method in which the conventional semiconductor device is provided with an auxiliary circuit (not shown) such as an address counter, and stress is applied to the entire area of the memory 2 by counting up the address counter or the like. In this method, however, when a lot of memory circuits and analog circuits as test targets are mounted on a system LSI under test, more auxiliary circuits as described above are required, and the chip area increases in proportion to the number of the auxiliary circuits to be mounted, and therefore, miniaturization of the chip cannot be achieved. Furthermore, it is necessary to perform a test on the auxiliary circuits in addition to the ordinary test, resulting in a problem concerning the tests, i.e., increased time and cost for the tests.
The present invention is made to solve the above-described problems and has for its object to provide a semiconductor device performing a burn-in test using scan chains, which semiconductor device can reliably apply stress to a target circuit to be tested, such as a memory, during the burn-in test, without requiring auxiliary circuits for stress application.
Other objects and advantages of the invention will become apparent from the detailed description that follows. The detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the scope of the invention will be apparent to those of skill in the art from the detailed description.
According to a first aspect of the present invention, there is provided a semiconductor device comprising: a test circuit to be subjected to a test; plural flip-flops which are connected in a scan chain; and a selector circuit for receiving the outputs from the plural flip-flops, add the outputs from combinational circuits which receive the outputs from the plural flip-flops, selecting the outputs from the plural flip-flops as test signals when the semiconductor device is in a test mode, and outputting the test signals to the test circuit, thereby to operate the test circuit. Therefore, stress can be easily and reliably applied to the test circuit without increasing auxiliary circuits for stress application when a burn-in test is carried out. Further, since a control circuit for controlling the selector circuit is controlled using an external input terminal group, the circuit structure of the control circuit is easily realized.
According to a second aspect of the present invention, the semiconductor device according to the fir t aspect further comprises a control circuit for outputting plural control signals for controlling the selecting operation of the selector circuit; and the control circuit has a decoder circuit for decoding signals of predetermined contents, which are supplied from the outside, and outputting signals corresponding to the contents of the decoded signals, as the control signals, to the selector circuit. Therefore, the number of external input terminals connected to the control circuit is reduced, and the circuit structure of the control circuit is easily realized.
According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the control circuit further includes plural flip-flops which are connected in a scan chain, and the flip-flops hold the signals supplied from the outside, and output the signals to the decoder circuit. Therefore, the number of external input terminals is further reduced, and it is particularly effective in performing a wafer-level burn-in test or the like in which the number of probes or the like is restricted. Further, since the area of the control circuit is reduced, the chip area of the semiconductor device is reduced.
According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the selector circuit comprises: first selectors for receiving the outputs from the plural flip-flops and thy outputs from the combinational circuits, selecting the outputs from the plural flip-flops as the test signals during the test mode, and outputting the test signals to the test circuit, thereby to operate the test circuit; and second selectors for receiving the outputs from the plural flip-flops and the outputs from the flip-flops in the stages previous to the respective flip-flops, selecting the outputs from the respective flip-flops during the test mode, thereby to make the respective flip-flops maintain the present values. Therefore, adjustment of clock timings among the respective flip-flops is facilitated.
According to a fifth aspect of the present invention, in the semiconductor device according to the first aspect, the plural flip-flops are operated on the basis of a clock signal supplied from the outside; and the semiconductor device further includes a logic gate circuit for stopping the supply of the clock signal during the test mode, thereby to make the respective flip-flops maintain the present values. Therefore, the construction for holding the output values is easily realized.
According to a sixth aspect of the present invention, in the semiconductor device according to the first aspect, the selector circuit includes a data generation circuit for counting up or down the values which are held by N (N: natural number) flip-flops among the plural flip-flops, according to a clock signal supplied from the outside, and outputting the counted up or down values held by the N flip-flops as the test signals to the test circuit, thereby to operate the test circuit. Therefore, stress can be applied to all combinations of addresses in the test circuit, or all write data, without setting data on the respective flip-flops in the scan chain, whereby control of the semiconductor device is facilitated.
According to a seventh aspect of the present invention, in the semiconductor device according to the sixth aspect, the data generation circuit comprises: first selectors for receiving the outputs from the N flip-flops, and the outputs from N combinational circuits which receive the outputs from the N flip-flops, selecting the outputs from the respective flip-flops as the test signals during the test mode, and outputting the test signals to the test circuit, thereby to operate the test circuit; a second selector for a least significant bit, which receives the output from a NOT circuit that receives the output from a flip-flop for a least significant bit, and the output from a flip-flop in the stage previous to the flip-flop for the least significant bit, among the N flip-flops; and second selectors for bits other than the least significant bit, which receives the outputs from an EX13OR circuit that receives the outputs from (Nxe2x88x921) flip-flops for the bits other than the least significant bit, and the outputs from the flip-flops in the stages previous to the (Nxe2x88x921) flip-flops, among the N flip-flops. Therefore, when the semiconductor device is in the test mode, stress can be applied to the test circuit without setting data on the respective flip-flops by scan shift, whereby control of the semiconductor device is facilitated.
According to an eighth aspect of the present invention, in the semiconductor device according to the sixth aspect, when the semiconductor device is in the test mode, the data generation circuit sets an address of N bits of the test circuit, which address is to be inputted as one of the test signals. Therefore, stress can be applied to all combinations of addresses in the test circuit, without setting data on the respective flip-flops in the scan chain, whereby control of the semiconductor device is facilitated.
According to a ninth aspect of the present invention, in the semiconductor device according to the sixth aspect, when the semiconductor device is in the test mode, the data generation circuit sets a data value of N bits of the test circuit, which data value is to be inputted as one of the test signals. Therefore, stress can be applied to all write data in the test circuit, without setting data on the respective flip-flops in the scan chain, whereby control of the semiconductor device is facilitated.
According to a tenth aspect of the present invention, in the semiconductor device according to the first aspect, the test circuit is a memory. Therefore, when the semiconductor device performs a burn-in test, stress can be easily applied to the memory as a circuit to he tested, without adding a circuit dedicated to the test only.
According to an eleventh aspect of the present invention, in the semiconductor device according to the first aspect, the test circuit is an analog circuit to which digital signals can be inputted. Therefore, when the semiconductor device performs a burn-in test, stress can be easily applied to the analog circuit as a circuit to be tested, without adding a circuit dedicated to the test only.